this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 03 / jun. 2000 hyundai semiconductor hy628400 a series 512kx8bit cmos sram description the hy628400 a is a high-speed, low power and 4m bits cmos sram organized as 512k words by 8 bits. the hy628400 a uses hyundai's high performance twin tub cmos process technology and was designed for high-speed and low power circuit technology. it is particularly well suited for use in high-density and low power system applications. this device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0v. features fully static operation and tri-state outputs ttl compatible inputs and outputs low power consumption battery backup(l/ll-part) - . 2.0v(min) data retention standard pin configuration - . 32pin 525mil sop - . 32pin 400mil tsop-ii (standard and reversed) product voltage speed operation standby current( ua) temperature no. (v) ( ns) current / icc ( ma) l ll ( c ) hy628400 a 4.5~5 . 5 55/70/85 10 100 30 0~70 note 1. current value is max. pin connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss a17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 a17 a17 vcc a15 /we a13 a8 a9 a11 /oe a10 /cs i/o8 i/o7 i/o6 i/o5 i/o4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss sop tsopii(standard) tsopii(reversed) pin description block diagram pin name pin function /cs chip select /we write enable /oe output enable a0 ~ a18 address input s i/o1 ~ i/o8 data input s /output s vcc power( 4.5~5.5 v) vss ground memory array 512kx 8 row decoder sense amp write driver data i/o buffer i/o1 i/o8 column decoder add input buffer a0 a18 /cs /oe /we control logic
hy628400 a series rev. 0 3 / jun. 2000 2 ordering information part no. speed power temp package hy628400 a lg 55/70/85 l-part sop hy628400 a llg 55/70/85 ll-part sop hy628400 a lt2 55/70/85 l-part tsop-ii(standard) hy628400 a llt2 55/70/85 ll-part tsop-ii(standard) hy628400 a lr2 55/70/85 l-part tsop-ii(reversed) hy628400 a llr2 55/70/85 ll-part tsop-ii(reversed) absolute maximum rating (1) symbol parameter rating unit remark vcc, v in, v out power supply, input/output voltage -0.5 to 7.0 v t a operating temperature 0 to 70 c hy628400 a t stg storage temperature -65 to 125 c p d power dissipation 1.0 w t solder lead soldering temperature & time 260 10 c sec note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliablity. truth table /cs /we /oe mode i/o operation power h x x deselected high-z standby l h h output disabled high-z active l h l read data out active l l x write data in active note : 1. h=v ih , l=v il , x=don't care ( v ih or v il )
hy628400 a series rev. 0 3 / jun. 2000 3 recommended dc operating condition t a =0 ? to 70 ? (normal) symbol parameter min. typ. max. unit vcc supply voltage 4.5 5.0 5.5 v vss ground 0 0 0 v v ih input high voltage 2.2 - vcc+0.5 v v il input low voltage -0.5 (1) - 0.8 v note : 1. v il = -1.5v for pulse width less than 30ns and not 100% tested. dc electrical characteristics t a = 0 c to 70 c unless otherwise specified symbol parameter test condition min . typ . max . unit i li input leakage current vss < v in < vcc -1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il -1 - 1 ua icc operating power supply current /cs = v il , v in = v ih or v il, i i/o = 0ma - 10 ma i cc1 average operating current /cs = v il min duty cycle = 100%, v in = v ih or v il, i i/o = 0ma - 60 ma i sb ttl standby current (ttl input) /cs = v ih - 2 ma i sb1 /cs > vcc - 0.2v l - - 100 ua standby current (cmos input) ll - - 30 ua v ol output low voltage i ol = 2.1ma - - 0.4 v v oh output high voltage i oh = -1ma 2.4 - - v note : typical values are at vcc = 5.0v, t a = 25 c capacitance temp = 25 c , f= 1.0mhz symbol parameter condition max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v i/o = 0v 8 pf note : this parameter is sampled and not 100% tested
hy628400 a series rev. 0 3 / jun. 2000 4 ac characteristics t a = 0 c to 70 c unless otherwise specified 55 ns 70 ns 85 ns min. max. min. max. min max. 1 trc read cycle time 55 - 70 - 85 - ns 2 taa address access time - 55 - 70 - 85 ns 3 tacs chip select access time - 55 - 70 - 85 ns 4 toe output enable to output valid - 25 - 40 - 45 ns 5 tclz chip select to output in low z 10 - 10 - 10 - ns 6 tolz output enable to output in low z 5 - 5 - 5 - ns 7 tchz chip deselecting to output in high z 0 20 0 25 0 30 ns 8 tohz out disable to output in high z 0 20 0 25 0 30 ns 9 toh output hold from address change 10 - 10 - 10 - ns 10 twc write cycle time 55 - 70 - 85 - ns 11 tcw chip selection to end of write 45 - 60 - 70 - ns 12 taw address valid to end of write 45 - 60 - 70 - ns 13 tas address set-up time 0 - 0 - 0 - ns 14 twp write pulse width 40 - 50 - 55 - ns 15 twr write recovery time 0 - 0 - 0 - ns 16 twhz write to output in high z 0 20 0 25 0 30 ns 17 tdw data to write time overlap 25 - 30 - 40 - ns 18 tdh data hold from write time 0 - 0 - 0 - ns 19 tow output active from end of write 5 - 5 - 5 - ns ac test conditions t a = 0 c to 70 c unless otherwise specified parameter value input pulse level 0.8v to 2.4v input rise and fall time 5ns input and output timing reference level 1.5v output load cl = 100pf + 1ttl load ac test loads cl(1) ttl note 1. including jig and scope capacitance read cycle write cycle symbol parameter # unit
hy628400 a series rev. 0 3 / jun. 2000 5 timing diagram read cycle 1(note 1 ,4 ) read cycle 2(note 1,2, 4 ) trc taa data valid previous data toh toh addr data out read cycle 3(note 1, 2, 4) /cs tacs data valid tclz(3) tchz(3) data out notes: 1. read cycle occurs whenever a high on the /we and /oe is low, and / cs are in active status. 2. /oe = v il 3. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. /cs in high for the standby, low for active addr trc / cs taa tacs toh data valid high-z data out / oe toe tclz (3) t olz (3) t chz (3) tohz (3)
hy628400 a series rev. 0 3 / jun. 2000 6 write cycle 1 (1,4,5,9) (/we controlled) write cycle 2 (note 1,4, 5 ,9 ) (/cs controlled) data valid addr data out / cs / we twc tcw twr (2) taw twp data in high-z tas twhz (3,8) tdw tdh tow (6) (7) data valid addr data out / cs / we twc tcw twr (2) taw twp data in tdw tdh high-z high-z tas
hy628400 a series rev. 0 3 / jun. 2000 7 notes: 1. a write occurs whenever a low on the /we and /oe is low while /cs are in active state. 2. twr is measured from the earlier of /cs or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. /oe is continuously low(/oe=v il ) 6. q(data out) is the same phase with the write data of this write cycle. 7. q(data out) is the read data of the next address. 8. transition is measured + 200mv from steady state. this parameter is sampled and not 100% tested. 9. /cs in high for the standby, low for active data retention electric charateristic t a =0 c to 70 c (normal) symbol parameter test condition min typ max unit v dr vcc for data retention /cs > vcc - 0.2v 2.0 - - v vss < v in < vcc i ccdr vcc = 3.0v, l - - 50 ua /cs > vcc - 0.2v ll - - 15 ua data retention current vss < v in < vcc tcdr chip deselect to data retention time 0 - - ns tr operating recovery time trc(2) - - ns notes: 1. typical values are at the condition of t a = 25 c . 2. trc is read cycle time. data retention timing diagram / cs vdr / cs > vcc-0.2v tcdr tr vss vcc 4.5v 2.2v data retention mode
hy628400 a series rev. 0 3 / jun. 2000 8 package information 32pin 400mil thin small outline package standard(t2) 0.404(10.2620) 0.396(10.0580() 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) 0.050bsc (1.2700) 0.017(0.4500) 0.012(0.3050) base plane seating plane 0.047(1.1940) 0.039(0.9910) 0.0059(0.1500) 0.0020(0.0500) 0.0083(0.2100) 0.0047(0.1200) 0.0235(0.5970) 0.0160(0.4060) gage plane 0-5 unit : inch(mm) max. min. 32pin 400mil thin small outline package reversed(r2) 0.404(10.2620) 0.396(10.0580) 0.470(11.9380) 0.462(11.7350) 0.829(21.0570) 0.822(20.8790) 0.050 bsc (1.2700) 0.017(0.4500) 0.012(0.3050) base plane seating plane 0.047(1.1940) 0.039(0.9910) 0.0059(0.1500) 0.0020(0.0500) 0.0083(0.2100) 0.0047(0.1200) 0.0235(0.5970) 0.0160(0.4060) gage plane 0-5 unit : inch(mm) max. min.
hy628400 a series rev. 0 3 / jun. 2000 9 32pin 525mil small outline package(g) unit : inch(mm) 0.444(11.27 8 ) 0.438(11.125) 0.564(14.326) 0.546(13.868) 0.810(20.574) 0.804(20.42 2 ) 0.109(2.769) 0.099(2.515) 0.011(0.279) 0.004(0.10 2 ) 0.020(0.508) 0.014(0.356) 0.050(1.27)bsc 0.0125(0.318) 0.0061(0.155) 0.0425(1.0 80 ) 0.0235(0.59 7 ) 0 deg 8 deg
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